Current & Next FPGA CPU Models

Features Of The 210

• Builds on my gen1cpu and the “200 Series” (gen2cpu) branch with improved cross-compatibility between configurations
• Native code built for either the 32-bit or 64-bit configuration can launch correctly on the opposite configuration
• This does not include full maths compatibility and compatibility between all extra features, only basic ISA & function call ABI cross-compatibility
• Maths still happens in 32-bit mode on 32-bit cores and 64-mode on 64-bit cores, but whether the extended bits are available can be easily detected in code
• These features are not properly tested in this version, and should be considered experimental for now

Possible Features (~220)

• Improved testing & FPGA support
• Will hopefully be tested & working on more different FPGA devices
• More/easier/faster memory access on common FPGA models, hopefully
• Possibly more I/O
• Huge overhaul of RISC Emulation
• This could include limited support for instruction sets of planned secondary processor lines