Author: admin

A Word On Consulting

I can offer general services relating to my product range, I don’t want to be a consultancy business though. My ambition is for finished products and my circumstances don’t adapt well to easily attracting clients for one off jobs, I’m stuck out of town for now so it’s easier to just create & export products.

Soft CPUs For FPGA

This will probably be my main product, I know it’s a bit saturated but frankly I don’t really care unless anybody can actually compete with me in bundled extras & quality control. I think I can clean the floor in this category if I put enough work in (not there yet though!).

• The 200/210 architecture will remain as my small in-house design (currently only suited to simple or hobby uses)
• The 305/306+ models will be my larger scale devices, these will be scalable & competitive for typical FPGA uses once I’ve improved them some more (these are based on third party designs which have been heavily extended)

These products are already demonstrable but a bit rough around the edges, I can take orders now if people are interested but there will be some more specific configurations advertised in a month or two, maybe with their own board designs or maybe targeted at commodity FPGA dev boards.

Hardware Components & Manufacturing Platform

This will involve small manufacturing runs using customised equipment, and will utilise the existing SecureLang® operating system which will be customised for testbench & hardware development workflows.

This won’t be aimed at mass production in my own workshop but will produce sample units and equipment/techniques for manufacturing, initially of simpler items such as individual transistors.

A particular focus of this product range will be helping to bootstrap manufacturing industries closer to mining areas/communities in Africa, Australia & elsewhere.

Reduced Software Focus (The Story)

I managed to finish most of my planned software and will be making good use of it with my hardware range.

I got disrespected greatly by a lot of people locally while I was just trying to invite people to demos and finish my code. Obviously people seem to think “programmer” means someone they can mock and threaten and rob and spread rumours about without consequences.

So from now on I’m going to be dealing with furnaces that are pretty hot, probably some high voltage equipment, really expensive materials that you probably don’t want getting in your eyes. And if anyone tries to fucking jump me by surprise with some junkie shit again while I’m trying to work and that person gets burnt that is their own problem.

It’s still early days but it looks like I can now confirm that – in the final hours, just as I was preparing to give up – my experiments in larger processors have been a success.

The 305/306 models are now working on at least one FPGA device, but the extensions and tuning are nowhere near complete.

Features (Working)

• Five-stage, single-issue pipeline
• RV64I instruction set

Features (Broken)

• An optional six-stage pipelined version exists, this actually does work in simple tests but doesn’t pass any reasonable timing constraints
• Hardware threading is currently completely broken on FPGA, builds with this feature are still fine in simulation but collapse when attempted in FPGA (this is probably just a small bug, missing some connections that the simulator ignores but hardware can’t)

Features (Untested)

• Some other classical optimisations exist but haven’t been fully tested on FPGA yet
• This includes register windows and delay slot execution (which can optimise simpler builds but is less useful in maxed out builds)

Other Plans

Once fixed up this should be great for extreme scale as you can just configure options to make an end device with as many hardware threads as you like. But, I need something faster too…

This will probably involve pairing a superscalar core with the scalable threaded core, this plan gives you multidimensional scalability as you can configure chips that run individual programs faster and/or also allow many efficient parallel threads.

More To Come…

There will probably be an official dev board combining my CPU, peripherals and operating system boot environment.

This Is A Bit Less Easy.

Smaller CPU designs are fairly easy to work with and will work on convenient FPGA boards.

Larger designs have proven a pain to get working on FPGAs. There are a lot of issues with larger FPGAs to the extent that I’d recommend starting CPU development on an underpowered one.

Issues with running designs on larger FPGAs include:

• Harder to get the tools working, will need to create accounts on very broken vendor websites to access downloads
• Documentation is fucked, I don’t know who they expect to be buying these things but printing a pinout with the boards would be fucking nice
• Examples that don’t work, tools that give warnings when you do things the example way, a weird sensation like the vendor didn’t actually want to sell you this product…

I won’t point out any specific vendors but basically they are all a bit shit (although their support teams can be helpful!), unless you buy the cheap models that are easy to program from a Linux terminal. With those you’re just a bit limited in the size of the design, they will only fit a simple CPU.

It Works In Simulation

It’s been easier to get features working in simulation though, so in a Verilog simulator my new design has the following features:

• Modern 64-bit RISC architecture
• 5-stage or (experimental) 6-stage pipeline
• Extremely efficient hardware threads implementation, designed for configurations with 4 threads per core
• Alternative optimisations for efficient/fast single-threaded implementations
• Very suitable for real-time device control or for further extension as server CPUs
• Based on a simpler MIT-licensed design, allowing for relatively easy commercial or open source licensing

Long Way To Go…

The current design looks and feels really solid, in simulation… There is no guarantee that it will ever work in hardware, maybe I will have to go back to the drawing board eventually but until then I’m working around the clock to make this design work.

There’s a chance that it will just work effortlessly in FPGA & in silicon once I figure out one more bug or get one more FPGA board working, but realistically it’ll take quite a lot more optimisation to get it fine tuned and also to add all the extensions developers would want.

Full Announcement Forthcoming

So I don’t know if this all is going to work right yet, I will reserve more detailed announcements until later.

If my new design does work this will probably become the basis for testing & deploying my OS code, otherwise the backup plan is I’ll probably scale back a little on my hardware designs and offer software/configuration support for existing designs instead (this will probably mean some less aggressive open source CPU forks). But for now of course I’ll continue working on bringing up this design on FPGA, which should work if I spend enough time isolating & testing each behaviour (my current testbench is just a bit of a mess).

So something will be coming either way, but for now I’m slowly progressing on the larger model which should perform quite well on large FPGAs if I can iron out the remaining bugs. This won’t be completely full-featured at first but should provide a good basis for extension.

Work on a larger CPU family utilising both new and legacy designs is underway. Proper announcements will follow.

The 210 Works On More FPGAs

The latest configuration has been tested on GateMate FPGAs and results in working builds (as determined by running a simple “flashing LEDs” program). This means that Gowin and GateMate are now supported targets, although it’ll take me a little while to clean up & extend the builds.

Higher-End Models Underway

I should have some faster base models uploaded soon based on third-party open source projects. So these initial models will represent much less engineering effort at my end but will hopefully form the basis of a stable processor lineup: hardened & supported versions of existing designs.

This currently involves experimenting with two different open-source designs, and provided that the basics eventually work I should be able to start uploading my changes soon.

Note that model numbers will not indicate newness but should roughly correspond to size of the design, and that the level of support I can offer won’t be exactly the same for each model (although at least some of my compilers will be portable to each).

Having To Think About Version Control…

I may just go back to using git as this seems easier for browsing projects & READMEs online, or I may release more over SVN as this is very convenient from my end.

Features Of The 210

• Builds on my gen1cpu and the “200 Series” (gen2cpu) branch with improved cross-compatibility between configurations
• Native code built for either the 32-bit or 64-bit configuration can launch correctly on the opposite configuration
• This does not include full maths compatibility and compatibility between all extra features, only basic ISA & function call ABI cross-compatibility
• Maths still happens in 32-bit mode on 32-bit cores and 64-mode on 64-bit cores, but whether the extended bits are available can be easily detected in code
• These features are not properly tested in this version, and should be considered experimental for now

Possible Features (~220)

• Improved testing & FPGA support
• Will hopefully be tested & working on more different FPGA devices
• More/easier/faster memory access on common FPGA models, hopefully
• Possibly more I/O
• Huge overhaul of RISC Emulation
• This could include limited support for instruction sets of planned secondary processor lines

Model Numbers <100

These will be extra lightweight models designed to fit on practically any FPGA (a few thousand LUTs?) but may not offer modern CPU functionality (e.g. may be 16-bit designs).

Models ≥100 and <1000

These will be the primary models designed for beginner FPGA users (i.e. the range surrounding the current 200/210 model).

These will be 32-bit and 64-bit models targeted at the best FPGAs for beginners, and will need at least around 10,000 LUTs depending on model or configuration.

Models ≥1000

These will be the high-performance and/or legacy-compatible models, which will probably mostly be based on existing open source projects.

Following the first release of my second-generation processor architecture I’ve got a new update improving software cross-compatibility between 32-bit and 64-bit configurations.

This works by providing multiple instructions for reading/writing 32-bit chunks of data which can be ignored or interpreted differently when run on different processor configurations, allowing programs optimised for either target to launch smoothly and detect the environment when run on either a 32-bit or 64-bit core.

Although other features necessary for a viable CPU are still in progress, I hope to continue improving the core architecture and amplify key features like this which each update!

This update is in the final stages now and only represents a minor mechanical change with minimal testing but hopefully will be a major improvement to cross-compatibility between future models.

Brief Announcement

I’ve released a second-generation version of my processor core, this has some advanced CPU-like features but is suited for use with FPGA technology as a microcontroller.

After rigorous improvements still following from my original design, this version is now beginning to work in a more robust way and is now tested using compiled program code (the design is now stable enough to run loops & function calls).

Introductory Branding

The processor architecture will for now be referred to as the SecureLang® 200 or The SecureLang® 200 Series Microcontroller Architecture, in reference to each current version being a revision of the second generation processor design.

The current revisions may be called 204, 205, 206 and so on until a new major iteration, while some early documentation may refer to the architecture as 232 or 264 based on bit width.

The repository names are gen1cpu for the original (first-generation) version which can be found in a probably-broken form on GitHub and gen2cpu for the current 200 Series which is released over subversion. Open-source forks can use the genNcpu naming to refer to their or my freely available versions if they prefer to avoid any commercial branding.

Software Still In Progress

Only my Pascal-like subsystem fully supports the new CPU architecture at present, announcements about the operating system in general will treat it as a separate product for now.

Base Version Will Remain Free

The initial version of my processor design was made available freely and this will continue to apply to basic versions of the design.

Hardware Out Now (Only Catch Is…)

The latest versions of the design have already been released, current public releases are made over Subversion to see if this convenient:

https://svn.riouxsvn.com/gen2cpu/

The only catch is that this (second) version is still a very early test design which is only suited for use using FPGA devices or simulators. As such this version still has somewhat limited performance, but otherwise should be near to being a stable product.

For now this means you will need a SiPEED Tang Nano 20K device or comparable/better FPGA device and/or a laptop to test the design.

Hardware Specs

• Developed in Verilog for easy use on FPGAs
• Low footprint, requires <10,000 LUTs
• Supported by efficient, in-house compiler technology
• Available in both 32-bit and 64-bit configurations
• Optional management & emulation features
• Custom instruction set allowing up to 256 registers
• Limited but reasonable runtime performance (no advanced pipelining or caching features)

I’ve been working these CPUs a little hard, some big little things are coming to replace them.