SecureLang® 200

Brief Announcement

I’ve released a second-generation version of my processor core, this has some advanced CPU-like features but is suited for use with FPGA technology as a microcontroller.

After rigorous improvements still following from my original design, this version is now beginning to work in a more robust way and is now tested using compiled program code (the design is now stable enough to run loops & function calls).

Introductory Branding

The processor architecture will for now be referred to as the SecureLang® 200 or The SecureLang® 200 Series Microcontroller Architecture, in reference to each current version being a revision of the second generation processor design.

The current revisions may be called 204, 205, 206 and so on until a new major iteration, while some early documentation may refer to the architecture as 232 or 264 based on bit width.

The repository names are gen1cpu for the original (first-generation) version which can be found in a probably-broken form on GitHub and gen2cpu for the current 200 Series which is released over subversion. Open-source forks can use the genNcpu naming to refer to their or my freely available versions if they prefer to avoid any commercial branding.

Software Still In Progress

Only my Pascal-like subsystem fully supports the new CPU architecture at present, announcements about the operating system in general will treat it as a separate product for now.

Base Version Will Remain Free

The initial version of my processor design was made available freely and this will continue to apply to basic versions of the design.

Hardware Out Now (Only Catch Is…)

The latest versions of the design have already been released, current public releases are made over Subversion to see if this convenient:

https://svn.riouxsvn.com/gen2cpu/

The only catch is that this (second) version is still a very early test design which is only suited for use using FPGA devices or simulators. As such this version still has somewhat limited performance, but otherwise should be near to being a stable product.

For now this means you will need a SiPEED Tang Nano 20K device or comparable/better FPGA device and/or a laptop to test the design.

Hardware Specs

• Developed in Verilog for easy use on FPGAs
• Low footprint, requires <10,000 LUTs
• Supported by efficient, in-house compiler technology
• Available in both 32-bit and 64-bit configurations
• Optional management & emulation features
• Custom instruction set allowing up to 256 registers
• Limited but reasonable runtime performance (no advanced pipelining or caching features)