I’m very excited about current progress.
Very early multi-core tests are functioning but with limited integration. Early tests show 8 LEDs being activated with reliable timing, each LED controlled by a program running in an individual hardware thread across 2 CPU cores on FPGA.
This means that what is now working is multiple CPU cores with multiple hardware threads per core (building on my work on hardware multithreading in the last updates) and this is working on reasonably small FPGAs with 2 cores & 4 threads per core (8 hardware threads total), but there is no standard interface for interaction between cores & threads yet to run a sensible operating system & start/stop/debug programs after boot.
So by adjusting the configurations in different ways, I should be able to make relatively efficient use of FPGA space (or maybe later custom silicon area) providing a near maximum of multiprocessing throughput to fit any reasonable volume of electronic space. This logic only currently applies to simplistic programs though, it doesn’t have full compute extensions like FPU or MMU for complex software packages at this stage!
Leave a Reply