It’s still early days but it looks like I can now confirm that – in the final hours, just as I was preparing to give up – my experiments in larger processors have been a success.
The 305/306 models are now working on at least one FPGA device, but the extensions and tuning are nowhere near complete.
Features (Working)
- Five-stage, single-issue pipeline
- RV64I instruction set
Features (Broken)
- An optional six-stage pipelined version exists, this actually does work in simple tests but doesn’t pass any reasonable timing constraints
- Hardware threading is currently completely broken on FPGA, builds with this feature are still fine in simulation but collapse when attempted in FPGA (this is probably just a small bug, missing some connections that the simulator ignores but hardware can’t)
Features (Untested)
- Some other classical optimisations exist but haven’t been fully tested on FPGA yet
- This includes register windows and delay slot execution (which can optimise simpler builds but is less useful in maxed out builds)
Other Plans
Once fixed up this should be great for extreme scale as you can just configure options to make an end device with as many hardware threads as you like. But, I need something faster too…
This will probably involve pairing a superscalar core with the scalable threaded core, this plan gives you multidimensional scalability as you can configure chips that run individual programs faster and/or also allow many efficient parallel threads.
More To Come…
There will probably be an official dev board combining my CPU, peripherals and operating system boot environment.
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