Currently in testing is multi-core support (working in simple tests) and boot-from-SD (not verified yet, but doesn’t break the build). Graphics & PC style I/O should come later.
My first attempt at a real multi-core bus with shared memory failed and just produced an unworkable version of the design so for now I’ve dropped back to testing simpler multi-core interactions and this is mostly going smoothly (it’s just a bit hard to tell what will fit on FPGAs in a complete design with all I/O attached). If the current design is mostly being synthesised in my tests (and not mostly being optimised away by FPGA tools) then this means I should be able to deploy functioning multi-core systems on common FPGA sizes, but otherwise it just means multi-core will only work in simpler examples or on top of the line FPGAs (which would’ve been my initial expectation anyway).
My current limitation is basically just fiddly hardware, I’ve got some really reliable FPGA boards with currently limited I/O and some bigger boards which in theory have all the I/O for testing but are absolute pains in the arse to program such as the tools only working on legacy PCs. The upside of this is that trying different boards instead of having one perfect kit (if any exist) lets me get a broad idea of the market for FPGA developer products and the current state of the art.
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