Subject to further testing, initial FPGA+LED tests are showing the current models booting and show some promise as becoming fully supported soft CPU models in the near future:
- 305, single-core, single-thread
- 306, single-core, single-thread
- 305, single-core, 4 threads
- 306, single-core, 4 threads
Current Model Naming
305 & 306 refers to the base pipeline. These are based on an open-source 5-stage 64-bit RISC design but with the 306 being extended with an additional maths stage. The 306 therefore is the more full featured but less stable option, the 305 base pipeline is relatively stable and runs okay on FPGA (306 currently has more timing issues, but basically works).
Single-threaded configurations are currently more stable/faster, this can be improved over time though. The main configuration of this design is intended to be 3 threads or 4 threads, configurations with 2 hardware threads or with more than 8 probably won’t be supported (the sweet spot for maximum throughput & efficiency is probably either 1, 3 or 4).
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