{"id":1349,"date":"2026-07-26T01:31:01","date_gmt":"2026-07-25T14:31:01","guid":{"rendered":"https:\/\/securelang.net\/cms\/?p=1349"},"modified":"2026-07-26T03:52:17","modified_gmt":"2026-07-25T16:52:17","slug":"bigger-cpu-simulation-phase","status":"publish","type":"post","link":"https:\/\/securelang.net\/cms\/blog\/2026\/07\/26\/bigger-cpu-simulation-phase\/","title":{"rendered":"Bigger CPU: Simulation Phase"},"content":{"rendered":"\n<h2 class=\"wp-block-heading\">This Is A Bit Less Easy.<\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">Smaller CPU designs are fairly easy to work with and will work on convenient FPGA boards.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Larger designs have proven a pain to get working on FPGAs. There are a lot of issues with larger FPGAs to the extent that I&#8217;d recommend starting CPU development on an underpowered one.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Issues with running designs on larger FPGAs include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Harder to get the tools working, will need to create accounts on very broken vendor websites to access downloads<\/li>\n\n\n\n<li>Documentation is fucked, I don&#8217;t know who they expect to be buying these things but printing a pinout with the boards would be fucking nice<\/li>\n\n\n\n<li>Examples that don&#8217;t work, tools that give warnings when you do things the example way, a weird sensation like the vendor didn&#8217;t actually want to sell you this product&#8230;<\/li>\n<\/ul>\n\n\n\n<p class=\"wp-block-paragraph\">I won&#8217;t point out any specific vendors but basically they are all a bit shit <em>(although their support teams can be helpful!)<\/em>, unless you buy the cheap models that are easy to program from a Linux terminal. With those you&#8217;re just a bit limited in the size of the design, they will only fit a simple CPU.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">It Works In Simulation<\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">It&#8217;s been easier to get features working in simulation though, so in a Verilog simulator my new design has the following features:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Modern 64-bit RISC architecture<\/li>\n\n\n\n<li>5-stage or (experimental) 6-stage pipeline<\/li>\n\n\n\n<li>Extremely efficient hardware threads implementation, designed for configurations with 4 threads per core<\/li>\n\n\n\n<li>Alternative optimisations for efficient\/fast single-threaded implementations<\/li>\n\n\n\n<li>Very suitable for real-time device control or for further extension as server CPUs<\/li>\n\n\n\n<li>Based on a simpler MIT-licensed design, allowing for relatively easy commercial or open source licensing<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">Long Way To Go&#8230;<\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">The current design looks and feels really solid, in simulation&#8230; There is no guarantee that it will ever work in hardware, maybe I will have to go back to the drawing board eventually but until then I&#8217;m working around the clock to make this design work.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">There&#8217;s a chance that it will just work effortlessly in FPGA &amp; in silicon once I figure out one more bug or get one more FPGA board working, but realistically it&#8217;ll take quite a lot more optimisation to get it fine tuned and also to add all the extensions developers would want.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Full Announcement Forthcoming<\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">So I don&#8217;t know if this all is going to work right yet, I will reserve more detailed announcements until later.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">If my new design does work this will probably become the basis for testing &amp; deploying my OS code, otherwise the backup plan is I&#8217;ll probably scale back a little on my hardware designs and offer software\/configuration support for existing designs instead (this will probably mean some less aggressive open source CPU forks). But for now of course I&#8217;ll continue working on bringing up this design on FPGA, which should work if I spend enough time isolating &amp; testing each behaviour (my current testbench is just a bit of a mess).<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">So something will be coming either way, but for now I&#8217;m slowly progressing on the larger model which should perform quite well on large FPGAs if I can iron out the remaining bugs. This won&#8217;t be completely full-featured at first but should provide a good basis for extension.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>This Is A Bit Less Easy. Smaller CPU designs are fairly easy to work with and will work on convenient FPGA boards. Larger designs have proven a pain to get working on FPGAs. There are a lot of issues with larger FPGAs to the extent that I&#8217;d recommend starting CPU development on an underpowered one. [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"pagelayer_contact_templates":[],"_pagelayer_content":"","footnotes":""},"categories":[1],"tags":[],"class_list":["post-1349","post","type-post","status-publish","format-standard","hentry","category-uncategorized"],"_links":{"self":[{"href":"https:\/\/securelang.net\/cms\/wp-json\/wp\/v2\/posts\/1349","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/securelang.net\/cms\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/securelang.net\/cms\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/securelang.net\/cms\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/securelang.net\/cms\/wp-json\/wp\/v2\/comments?post=1349"}],"version-history":[{"count":7,"href":"https:\/\/securelang.net\/cms\/wp-json\/wp\/v2\/posts\/1349\/revisions"}],"predecessor-version":[{"id":1360,"href":"https:\/\/securelang.net\/cms\/wp-json\/wp\/v2\/posts\/1349\/revisions\/1360"}],"wp:attachment":[{"href":"https:\/\/securelang.net\/cms\/wp-json\/wp\/v2\/media?parent=1349"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/securelang.net\/cms\/wp-json\/wp\/v2\/categories?post=1349"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/securelang.net\/cms\/wp-json\/wp\/v2\/tags?post=1349"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}