I’ve released a second-generation version of my processor core, this has some advanced CPU-like features but is suited for use with FPGA technology as a microcontroller.<\/p>\n\n\n\n
After rigorous improvements still following from my original design, this version is now beginning to work in a more robust way and is now tested using compiled program code (the design is now stable enough<\/strong> to run loops & function calls).<\/p>\n\n\n\n The processor architecture will for now be referred to as the SecureLang\u00ae 200<\/em> or The SecureLang\u00ae 200 Series Microcontroller Architecture<\/em>, in reference to each current version being a revision of the second generation processor design.<\/p>\n\n\n\n The current revisions may be called 204, 205, 206 and so on until a new major iteration, while some early documentation may refer to the architecture as 232 or 264 based on bit width.<\/p>\n\n\n\n The repository names are gen1cpu<\/em> for the original (first-generation) version which can be found in a probably-broken form on GitHub and gen2cpu<\/em> for the current 200 Series which is released over subversion. Open-source forks can use the genNcpu naming to refer to their or my freely available versions if they prefer to avoid any commercial branding.<\/p>\n\n\n\n Only my Pascal-like subsystem fully supports the new CPU architecture at present, announcements about the operating system in general will treat it as a separate product for now.<\/p>\n\n\n\n The initial version of my processor design was made available freely and this will continue to apply to basic versions of the design.<\/p>\n\n\n\n The latest versions of the design have already been released, current public releases are made over Subversion to see if this convenient:<\/p>\n\n\n\nIntroductory Branding<\/h2>\n\n\n\n
Software Still In Progress<\/h2>\n\n\n\n
Base Version Will Remain Free<\/h2>\n\n\n\n
Hardware Out Now (Only Catch Is…)<\/h2>\n\n\n\n