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Currently I’m working on getting a minimal PC style BIOS together and booting C code from my FPGA designs. This is separate to the customised C tool chain I use for 64-bit development, so I may release a fork of a legacy compiler (which is also a bit more complete than my own) to go with it.

Once this is complete I should be able to progress more rapidly with improved CPUs and then eventually with starting to port more of my operating system. The operating system won’t run on my current chipset though, I decided to moving to testing on smaller, 8-bit soft CPUs so I could ensure the base hardware & BIOS layers would be free from the pitfalls of larger CPUs.

This obviously doesn’t mean work on my 64-bit stack is obsolete or retired, just that I’ll finish some more basics before doing more work.

A NASA processor now being tested at JPL is performing 500 times faster than the radiation-hardened chips currently used in spaceflight — yet fits in the palm of a hand and could let future spacecraft make AI-powered decisions on their own when communicating with Earth can take 44 minutes round-trip.

I’ve crunched as many numbers as I can for now and it looks like full implementations of my larger CPU designs won’t fit on commodity FPGAs. Larger FPGAs will probably work for testing larger designs but those aren’t really practical for consumer FPGA-PC models.

Since the immediate goal is an operating system test rig, this probably means I’ll fall back to smaller and more well-proven/classic-style 32-bit designs.

Development of the larger CPU will remain active as I can probably continue with that on larger boards, it will just take a lower priority than getting a minimal working model out!

Every PC user today knows we kind of missed the peak, we didn’t appreciate what we had when computing could really be “personal”. The good news is there’s no longer a real technological moat around peak era PC technology, it’s relatively easy to build computers now (as can be seen from the amount of junk on the market). So today there are a lot of clones of old platforms, a few new ambitious platforms, but I’m not really seeing a lot in the middle that can replace legacy PC culture.

So, given that it’s really easy to get an ultra fast PC with all the latest AI stuff if you want that, and it’s really easy to get a clone of a vintage PC if you want that real retro experience, and given that these are widely available but often unaffordable or too risky of an investment, I think the gap in the market today might be for a “real” PC that actually lives up to the hype like “a computer all your own, controlled from your own home” and is a reliable recommendable product that won’t ruin your finances, career or hobby.

You are not alone. The current range of FPGA dev boards seem to be basically missing documentation and common sense. These things feel like they are designed by someone who hates beginners and is trying to gatekeep their own customer base. But if you just keep pushing, keep rebuilding in a different way when things break, I think it kind of works out eventually… I hope.

Reliable Releases

Binary releases will start once my hardware targets start to finalise. For each release there will probably be one CPU bitstream each for a couple of different FPGA developer boards, and probably one operating system SD image that should run on each different OS-capable configuration. Or otherwise maybe two OS builds, one with a simplified kernel.

Hardware Boards

These will start maybe around the end of the year, probably initially just as a test run to get some branded devices into existence. These will probably be similar to existing FPGA dev boards and probably based on existing open source designs, but will be customised for CPU+OS testing so should be a bit more usable like a mini PC out-of-the-box.

Graphics Demos

I’ve been promising graphics demos ever since finishing the kernel. The GUI kind of mostly works but won’t be able to be fully integrated with my hardware at this point.

So this means the full GUI system can be used for some tools on PC or for OS testing on commodity hardware but for real graphics demos showing my full stack I’ll have to go a little more retro for now (this might mean something like souped up VGA demos or something like a minimalist high-res GUI similar to legacy systems, but I won’t be able to do a full modern desktop with video/web/etc. running fully on my stack yet).

Actual Business Plan

Who knows?

I’ve been fucked around a lot the last couple of years so I’m currently stuck out of town with limited internet. This is okay for working on hardware and coordinating some business stuff, but I basically can’t offer services anymore as I just don’t have access to reliable services here. If the Australian housing crisis resolves itself any time in the near future then sure I hope to open a sprawling office in Sydney and take care of everybody’s shit for them so they can stop calling me lazy, otherwise I ain’t doing shit for people unless they provide accommodation/transport/snacks.

Assuming that I can get hardware in & out through the limited postal service though I can probably sell hardware devices and of course offer downloads online. So basically I’ll probably just aim to sell physical hardware.

Currently in testing is multi-core support (working in simple tests) and boot-from-SD (not verified yet, but doesn’t break the build). Graphics & PC style I/O should come later.

My first attempt at a real multi-core bus with shared memory failed and just produced an unworkable version of the design so for now I’ve dropped back to testing simpler multi-core interactions and this is mostly going smoothly (it’s just a bit hard to tell what will fit on FPGAs in a complete design with all I/O attached). If the current design is mostly being synthesised in my tests (and not mostly being optimised away by FPGA tools) then this means I should be able to deploy functioning multi-core systems on common FPGA sizes, but otherwise it just means multi-core will only work in simpler examples or on top of the line FPGAs (which would’ve been my initial expectation anyway).

My current limitation is basically just fiddly hardware, I’ve got some really reliable FPGA boards with currently limited I/O and some bigger boards which in theory have all the I/O for testing but are absolute pains in the arse to program such as the tools only working on legacy PCs. The upside of this is that trying different boards instead of having one perfect kit (if any exist) lets me get a broad idea of the market for FPGA developer products and the current state of the art.

Hardware State

The 305 CPU core is working very well and reliably in testing so far, I haven’t encountered any major issues since I originally got it working on FPGA (hopefully that was mostly just one-off problems).

Minor issues that can be improved from here are reducing some internal drag to allow for higher speeds and adding more extensions for easy CPU-style management & more optimisation. Customised MCU-like use cases where it launches a fixed program across some number of cores/threads seem to be stable even when pushing near the capacity of some FPGAs by maxing out the core count.

I’ve been testing across a range of cheap FPGAs and at least one model is very reliable with this design (more testing of this design on others will happen eventually).

Software State

The OS software, compilers etc. are still a little barebones but mostly working and ready to start porting to hardware. This may involve splitting parts of the OS into example code for embedded developers, or may involve a new version of the kernel built for my own configurations etc. The integration part isn’t complete yet but things like the filesystem could already be ported to the current soft CPU designs in theory.

Current Offering

I can sell you customised MCU units with customised software if you want (it’s just not well packaged into a complete set yet).

Packaged offerings will probably come later in the year.

I’m very excited about current progress.

Very early multi-core tests are functioning but with limited integration. Early tests show 8 LEDs being activated with reliable timing, each LED controlled by a program running in an individual hardware thread across 2 CPU cores on FPGA.

This means that what is now working is multiple CPU cores with multiple hardware threads per core (building on my work on hardware multithreading in the last updates) and this is working on reasonably small FPGAs with 2 cores & 4 threads per core (8 hardware threads total), but there is no standard interface for interaction between cores & threads yet to run a sensible operating system & start/stop/debug programs after boot.

So by adjusting the configurations in different ways, I should be able to make relatively efficient use of FPGA space (or maybe later custom silicon area) providing a near maximum of multiprocessing throughput to fit any reasonable volume of electronic space. This logic only currently applies to simplistic programs though, it doesn’t have full compute extensions like FPU or MMU for complex software packages at this stage!